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features ? fast read access time ? 70 ns low power cmos operation ?100 a max standby ? 30 ma max active at 5 mhz jedec standard packages ? 32-lead pdip ? 32-lead plcc ? 32-lead tsop 5v 10% supply high reliability cmos technology ? 2000v esd protection ? 200 ma latchup immunity rapid programming algorithm ? 100 s/byte (typical) cmos and ttl compatible inputs and outputs industrial temperature range green (pb/halide-free) packaging option 1. description the at27c040 chip is a low-power, high-performance, 4,194,304-bit one-time pro- grammable read-only memory (otp eprom) organized as 512k by 8 bits. the at27c040 requires only one 5v power supply in normal read mode operation. any byte can be accessed in less than 70 ns, eliminating the need for speed reducing wait states on high-performance microprocessor systems. atmel?s scaled cmos technology provides low active power consumption, and fast programming. power consumption is typically 8 ma in active mode and less than 10 a in standby mode. the at27c040 is available in a choice of industry-standard jedec-approved one- time programmable (otp) plastic pdip, plcc and tsop packages. the device fea- tures two-line control (ce , oe ) to eliminate bus contention in high-speed systems. atmel?s at27c040 has additional features to ensure high quality and efficient produc- tion use. the rapid programming algorithm reduces the time required to program the part and guarantees reliable programming. pr ogramming time is typically only 100 s/byte. the integrated product identification code electronically identifies the device and manufacturer. this feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. 4-megabit (512k x 8) otp eprom at27c040 0189g?eprom?05/05
2 0189g?eprom?05/05 at27c040 2.1 32-lead pdip top view 2.2 32-lead tsop top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vpp a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 o0 o1 o2 gnd vcc a18 a17 a14 a13 a8 a9 a11 oe a10 ce 07 06 05 04 03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 a18 vcc vpp a16 a15 a12 a7 a6 a5 a4 oe a10 ce 07 06 05 04 03 gnd 02 01 o0 a0 a1 a2 a3 2.3 32-lead plcc top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 o0 a14 a13 a8 a9 a11 oe a10 ce 07 4 3 2 1 32 31 30 14 15 16 17 18 19 20 01 02 gnd 03 04 05 06 a12 a15 a16 vpp vcc a18 a17 2. pin configurations pin name function a0 - a18 addresses o0 - o7 outputs ce chip enable oe output enable
3 0189g?eprom?05/05 at27c040 3. switching considerations switching between active and standby conditions via the chip enable pin may produce tran- sient voltage excursions. unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. at a minimum, a 0.1 f high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. this capacitor should be connected between the v cc and ground terminals of the device, as close to the device as possible. additionally, to stab ilize the supply voltage level on printed circuit boards with large eprom arrays, a 4.7 f bulk electrolytic capacitor should be utilized, again connected between the v cc and ground terminals. this capacitor should be positioned as close as possible to the point where the power supply is connected to the array. 4. block diagram 5. absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground ............................................-2.0v to +7.0v voltage on a9 with respect to ground .........................................-2.0v to +14.0v v pp supply voltage with respect to ground ..........................................-2.0v to +14.0v
4 0189g?eprom?05/05 at27c040 notes: 1. x can be v il or v ih . 2. refer to programming characteristics 3. v h = 12.0 0.5v. 4. two identifier bytes may be selected. all ai inputs are held low (v il ), except a9 which is set to v h and a0 which is toggled low (v il ) to select the manufacturer?s identification byte and high (v ih ) to select the device code byte. notes: 1. v cc must be applied simultaneously or before v pp , and removed simultaneously or after v pp . 2. v pp may be connected directly to v cc , except during programming. the supply current would then be the sum of i cc and i pp . 6. operating modes mode/pin ce oe ai v pp outputs read v il v il ai x (1) d out output disable x v ih xxhigh z standby v ih xxxhigh z rapid program (2) v il v ih ai v pp d in pgm verify x v il ai v pp d out pgm inhibit v ih v ih xv pp high z product identification (4) v il v il a9 = v h (3) a0 = v ih or v il a1 - a18 = v il x identification code 7. dc and ac operating conditions for read operation at27c040-70 at27c040-90 industrial operating temperature (case) -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% 8. dc and operating characteristics for read operation symbol parameter condition min max units i li input load current v in = 0v to v cc 1a i lo output leakage current v out = 0v to v cc 5a i pp1 (2) v pp (1) read/standby current v pp = v cc 10 a i sb v cc1 (1) standby current i sb1 (cmos), ce = v cc 0.3v 100 a i sb2 (ttl), ce = 2.0 to v cc + 0.5v 1 ma i cc v cc active current f = 5 mhz, i out = 0 ma, ce = v il 30 ma v il input low voltage -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 a 2.4 v
5 0189g?eprom?05/05 at27c040 note: 1. see ac waveforms for read operation 10. ac waveforms for read operation (1) notes: 1. timing measurement references are 0.8v and 2.0v. input ac drive levels are 0.45v and 2.4v, unless otherwise specified. 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce . 3. oe may be delayed up to t acc - t oe after the address is valid without impact on t acc . 4. this parameter is only sampled and is not 100% tested. 5. output float is defined as the point when data is no longer driven. 9. ac characteristics for read operation symbol parameter condition at27c040 units -70 -90 min max min max t acc (1) address to output delay ce = oe = v il 70 90 ns t ce (1) ce to output delay oe = v il 70 90 ns t oe (1) oe to output delay ce = v il 30 35 ns t df (1) oe or ce high to output float, whichever occurred first 20 20 ns t oh output hold from address, ce or oe , whichever occurred first 00 ns
6 0189g?eprom?05/05 at27c040 11. input test waveforms and measurement levels 12. output test load note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. output pin 1.3v (1n914) 3.3k cl 13. pin capacitance f = 1 mhz, t = 25 c (1) symbol typ max units conditions c in 48pfv in = 0v c out 812pfv out = 0v
7 0189g?eprom?05/05 at27c040 14. programming waveforms (1) notes: 1. the input timing reference is 0.8v for v il and 2.0v for v ih . 2. t oe and t dfp are characteristics of the device but must be accommodated by the programmer. 3. when programming the at27c040 a 0.1 f capacitor is required across v pp and ground to suppress spurious voltage transients.
8 0189g?eprom?05/05 at27c040 notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. this parameter is only sampled and is not 100% tested. output float is defined as the point where data is no longer driven ? see timing diagram. 3. program pulse width tolerance is 100 sec 5%. 15. dc programming characteristics t a = 25 5c, v cc = 6.5 0.25v, v pp = 13.0 0.25v symbol parameter test conditions limits units min max i li input load current v in = v il , v ih 10 a v il input low level -0.6 0.8 v v ih input high level 2.0 v cc + 0.7 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 a 2.4 v i cc2 v cc supply current (program and verify) 40 ma i pp2 v pp supply current ce = v il 20 ma v id a9 product identification voltage 11.5 12.5 v 16. ac programming characteristics t a = 25 5c, v cc = 6.5 0.25v, v pp = 13.0 0.25v symbol parameter test conditions (1) limits units min max t as address setup time input rise and fall times: (10% to 90%) 20 ns input pulse levels: 0.45v to 2.4v input timing reference level: 0.8v to 2.0v output timing reference level: 0.8v to 2.0v 2s t oes oe setup time 2 s t ds data setup time 2 s t ah address hold time 0 s t dh data hold time 2 s t dfp oe high to output float delay (2) 0 130 ns t vps v pp setup time 2 s t vcs v cc setup time 2 s t pw ce program pulse width (3) 95 105 s t oe data valid from oe (2) 150 ns t prt v pp pulse rise time during programming 50 ns 17. atmel?s at27c040 integrated product identification code codes pins hex data a0 o7 o6 o5 o4 o3 o2 o1 o0 manufacturer 000011110 1e device type 100001011 0b
9 0189g?eprom?05/05 at27c040 18. rapid programming algorithm a 100 s ce pulse width is used to program. the address is set to the first location. v cc is raised to 6.5v and v pp is raised to 13.0v. each address is first programmed with one 100 s ce pulse without verification. then a verification/reprogramming loop is executed for each address. in the event a byte fails to pass verification, up to 10 successive 100 s pulses are applied with a verification after each pulse. if the byte fails to verify after 10 pulses have been applied, the part is considered failed. after the byte verifies properly, the next address is selected until all have been checked. v pp is then lowered to 5.0v and v cc to 5.0v. all bytes are read again and compared with the original data to determine if the device passes or fails.
10 0189g?eprom?05/05 at27c040 19. ordering information note: refer to pcn# sc042702. 19.1 standard package t acc (ns) i cc (ma) ordering code package operation range active standby 70 30 0.1 at27c040-70ji at27c040-70pi at27c040-70ti 32j 32p6 32t industrial (-40 c to 85 c) 90 30 0.1 at27c040-90ji at27c040-90pi at27c040-90ti 32j 32p6 32t industrial (-40 c to 85 c) 19.2 green package option (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 70 30 0.1 at27c040-70ju at27c040-70pu at27c040-70tu 32j 32p6 32t industrial (-40 c to 85 c) 90 30 0.1 at27c040-90ju at27c040-90pu at27c040-90tu 32j 32p6 32t industrial (-40 c to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 32p6 32-lead, 0.600" wide, plastic dual inline package (pdip) 32t 32-lead, plastic thin small outline package (tsop)
11 0189g?eprom?05/05 at27c040 20. package information 20.1 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
12 0189g?eprom?05/05 at27c040 20.2 32p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32p6 , 32-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 32p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 41.783 ? 42.291 note 1 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 1 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
13 0189g?eprom?05/05 at27c040 20.3 32t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
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